The power efficiency of any device architecture is directly affected by its design. As the complexity, speed and density of the device architecture increases, the power consumption also increases. In particular, for FPGAs, it is essential to use a large number of switches and buffers to improve the signal strength. Although the FPGAs use low power technologies e.g. CMOS technology, the power consumption issue becomes one of the limiting factors. To avoid this, it is highly requisite to save undesired power leakage from various parts of the circuit.
The explosion in the market demand for wireless, battery powered products of all kinds has created a tremendous emphasis on battery life which is largely determined by leakage power in standby mode—the mode in which a portable system spends the majority of the time.
The present design of FPGAs allows a current leakage from different parts. For example, when the FPGA is not being used and the outputs/inputs of logic blocks are stuck at one value, there is no dynamic power consumption, but due to leakage currents there is a static power consumption. The leakage current depends on the device channel length, temperature and power supply. Since channel length cannot be changed once the device is fabricated and chips are made to be used in different temperature zones, no standard method can be developed for reducing the power leakage by controlling temperature and device channel length.
It is feasible to reduce static power consumption effectively by regulating/redistributing power supply. Reducing supply voltage in CMOS devices will reduce the leakage current, but in case of FPGAs the supply voltage cannot be reduced considerably as it results in a loss of information stored in the memory cells. Further reduction in the supply voltage does not eliminate leakage current totally from the circuit since it is not possible with the present design to disconnect the supply from elements which are not in use in the circuit. Moreover, different users require FPGAs with different power specifications.
Further recent demands for portable appliances such as laptop computers, cell phones or PDAs also fuel the need for low power designs of FPGAs to achieve longer battery life and miniaturization. One way to avoid wasting any current is to turn off the FPGA when it is not being used, but it requires reconfiguration of the FPGA for the next operation. This increases the complexity and timing of the system and uses more power because the FPGA consumes a good amount of power during configuration. Therefore, a need has arisen for an FPGA, which allows the user to reduce the power consumption without disturbing the programming information when the FPGA is not in use.